The present invention relates to semiconductor integrated circuit chip packages, and more particularly, to a technique for improving the bonding strength of the leadframe to substrate in semiconductor packages.
In recent years, semiconductor elements have been further advanced in their high density construction and it is increasingly more difficult to mount a semiconductor element directly on a printed wiring board or the like to construct various electronic equipment. In recent practice, thus, a semiconductor element is previously mounted for example on a board for mounting the electronic part to form a semiconductor device and such semiconductor device is then electrically connected to a printed wiring board using a surface mount technology or the like. Accordingly, proposals have been made of various boards for mounting electronic parts and of semiconductor devices using the same.
For example, for a semiconductor device internally having an electronic part mounting board integrating a leadframe and a printed wiring board, a circuit board with an electronic part attached thereto must be supported on the leadframe during the fabrication process of the semiconductor device, to connect the electronic part to leads of the leadframe by means of wire bonding. According to a conventional technology, supporting of a circuit board on a leadframe is performed by joining the lead terminals of the leadframe to the conductive layer on the circuit board by means of Pb/Sn solder, Au/Sn soldering, or other solder material commonly known to one skilled in the art.
FIGS. 1A and 1B illustrate two different types of conventional ETE (electrically and thermally enhanced) semiconductor packages. In FIG. 1A, each of the leadframe's bonding fingers 101 is electrically connected to a respective metallic trace 102 on the semiconductor substrate 106 using a plated through hole 103 and solder 108. The plated through hole (or via) is plated with an electrically conductive material which makes contact with a respective copper trace 102. A leadframe bonding finger 101 is then soldered to the plated through hole 103, thereby forming an electrical connection to the conductive trace 102.
In FIG. 1B, electrical connection is made from the leadframe finger 101 to the conductive trace 102 by physically bonding the leadframe finger to the conductive trace (at area 152) using a thermal compression bonding technique.
To use solder or soldering in coupling the circuit board and the leadframe, however, the junction must be heated at least to 200 degree(s) C. An ordinarily used board made of a resin may thus be deteriorated due to heat, or an internal stress may occur therein due to the fact that the thermal balance (i.e. CTE mismatch) between the circuit board and the leadframe cannot be maintained, resulting in such problems as that faults occur at the time of encapsulation and/or mounting the electronic part, thereby reducing the reliability of the finished product.
In the above conventional technique, there are the following additional problems:
(1) Both of electrical connecting function and physical holding function are generally included in the joint portion between the leadframe and the substrate. In the aforementioned conventional technique, it is expected to secure both of electrical connecting function and physical holding function in a joint portion of a main part only by soldering. Now, when such a joint portion is reviewed with respect to the leadframe for mounting high-performance semiconductor element, it is usually related to QFP (Quad Flat Package) capable of having input and output multi-terminals. In such a QFP structure, the joint portion is formed in the outer periphery of four sides, but means for releasing stress based on the difference in thermal expansion between the leadframe and the substrate is not formed, so that such a stress is stored in the joint portion. As a result, when conducting, for example, a life test of a final product, breakage is caused in the joint portion and hence breakage is caused in respective wiring portion.
(2) When the base material is joined to the leadframe through soldering, the joint portion is heated, but when the joint portion and the neighborhood thereof are returned to room temperature after the soldering, stress remains in the joint portion to cause undesirable situations such as warp, distortion and the like. In a step of mounting a semiconductor element, therefore, it is difficult or impossible to conduct the carrying and mounting operations of the semiconductor element due to the occurrence of warp and distortion, and consequently many inferior products are obtained. Additionally, in the conventional method, the lead is merely positioned to the substrate and is not fixed thereto. As a result, when the solder is returned from the heated state to room temperature, thermal stress is directly applied to the soldered joint between the lead and the through-hole, so that there is caused a fear of lowering the reliability in the soldered joint.
(3) In the joining between the leadframe and the substrate, it is necessary to conduct the positioning therebetween with a high accuracy in addition to given heating and pressurizing operations. In fact, the proper positioning is difficult to lower the yield in the joining.
It is therefore an object of the present invention to overcome the disadvantages described above, and to provide a new technique for improving the bonding strength of the leadframe to semiconductor substrate in semiconductor packages.